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[ak4118a] ms1130-e-02 2009/12 - 1 - general description the ak4118a is a digital audio transceiver supporting 192khz, 24bits. the channel status decoder supports both consumer and professional modes. the ak4118a can automatically detect a non-pcm bit stream. when combined with the multi channel codec (ak4626a or ak4628a), the two chips provide a system solution for ac-3 applications. the dedicated pins or a serial p i/f can control the mode setting. the small package, 48pin lqfp saves the system space. *ac-3 is a trademark of dolby laboratories. features ? aes3, iec60958, s/pdif, ei aj cp1201 compatible ? low jitter analog pll ? pll lock range: 8khz 192khz ? clock source: pll or x'tal ? 8-channel receiver input ? 2-channel transmission output (through output or dit) ? auxiliary digital input ? de-emphasis for 32khz, 44.1khz, 48khz and 96khz ? detection functions ? non-pcm bit stream detection ? dts-cd bit stream detection ? sampling frequency detection (32khz, 44.1khz, 48khz, 88.2khz, 96khz, 176.4khz, 192khz) ? unlock & parity error detection ? validity flag detection ? dat start id detection ? up to 24bit audio data format ? audio i/f: master or slave mode ? 42-bit channel status buffer ? burst preamble bit pc and pd buffer for non-pcm bit stream ? q-subcode buffer for cd bit stream ? serial p i/f (i 2 c, spi) ? two master clock outputs: 64fs/128fs/256fs/512fs ? operating voltage: 2.7 to 3.6v with 5v tolerance ? 8gpio port ? rx data input detection ? small package: 48pin lqfp ? ta: -10 to 70 c high feature 192khz 24bit di gital audio i/f transceiver ak4118a
[ak4118a] ms1130-e-02 2009/12 - 2 - block diagram in p ut selector clock recovery clock generator daif decoder ac-3/mpeg detect dem p i/f au dio i/f x'ta l oscillator pd n int0 p/s=?l? lrck bick sdto daux mcko2 xto xti r avd d av ss cdti cdto cclk csn dvdd dvss tvdd mcko1 iic rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 dit tx0 error & detect status int1 q-subcode bu ffer tx1 b,c,u,vout 8 to 3 vin gp0,1,2,3,4,5,6,7 serial control mode in p ut selector clock recovery clock generator daif decoder ac-3/mpeg detect dem au dio i/f x'ta l oscillator pd n int0 p/s=?h? lrck bick sdto daux xto xti r avd d av ss cm1 cm0 ock s 1 ock s 0 dvdd dvss tvdd ips1 rx0 rx1 rx2 rx3 ips0 dif0 dif1 dif2 dit tx0 error & detect status int1 tx1 b,c,u,vout 4 to 2 vin mcko2 mcko1 parallel control mode
[ak4118a] ms1130-e-02 2009/12 - 3 - ordering guide ak4118aeq -10 ~ +70 c 48pin lqfp (0.5mm pitch) AKD4118A evaluation board for ak4118a pin layout in t1 int0 3 7 av dd 3 6 3 8 r 3 9 vcom 4 0 vss3 4 1 rx0 4 2 nc 4 3 rx1 4 4 test1 4 5 rx2 4 6 vss4 ocks0/csn/cad0 35 ocks1/cclk/scl 3 4 33 32 pdn 31 xti 30 xt o 29 daux 28 mc ko2 27 bick 26 ips0/ rx4 1 nc 2 dif0/rx5 3 test2 4 dif1/rx6 5 6 dif2/rx7 7 ips1/iic 8 psn 9 xtl0 10 xtl1 11 24 23 22 21 20 19 18 17 16 15 14 lrck mcko1 vss2 dvdd vout/ gp7 uout/gp6 cout/gp5 bout/ gp4 tx1/gp3 tx0/gp2 gp1 ak4118aeq top view vss1 cm1/cdti/sd a cm0/cdto/cad1 sd to 25 vin/gp0 12 47 rx3 48 13 tvdd
[ak4118a] ms1130-e-02 2009/12 - 4 - compatibility with ak4118 1. function and characteristics function ak4118a ak4118 master clock the mcko2 pin outputs ?l? when cm1-0 bit = ?00?or ?10? and unlock bit = ?0?. the mcko1 and mcko2 pins output ?256fs, 128fs, 64fs? clock according to ocks1-0 bits setting, regardless of the clock source. s/pdif receiver time deviation jitter typ; 100ps rms cycle-to-cycle jitter typ; 50ps rms no descriptions about jitter. 2. register addr bit ak4118a ak4118 28h d6 1 0
[ak4118a] ms1130-e-02 2009/12 - 5 - pin/function no. pin name i/o function ips0 i input channel select 0 pin in parallel mode 1 rx4 i receiver channel 4 pin in seri al mode (internal biased pin) 2 nc i no connect no internal bonding. this pin should be connected to vss3. dif0 i audio data interface fo rmat 0 pin in parallel mode 3 rx5 i receiver channel 5 pin in seri al mode (internal biased pin) 4 test2 i test 2 pin this pin should be connect to vss3. dif1 i audio data interface fo rmat 1 pin in parallel mode 5 rx6 i receiver channel 6 pin in seri al mode (internal biased pin) 6 vss1 i ground pin dif2 i audio data interface fo rmat 2 pin in parallel mode 7 rx7 i receiver channel 7 pin in seri al mode (internal biased pin) ips1 i input channel select 1 pin in parallel mode 8 iic i iic select pin in serial mode. ?l?: 4-wire serial, ?h?: iic 9 psn i parallel/serial select pin ?l?: serial mode, ?h?: parallel mode 10 xtl0 i x?tal frequency select 0 pin 11 xtl1 i x?tal frequency select 1 pin vin i v-bit input pin for transmitter output 12 gp0 i/o gpio0 pin in serial mode 13 tvdd i input buffer power supply pin, dvdd ~5.5v 14 gp1 i/o gpio1 pin1in serial mode tx0 o transmit channel (through data) output 0 pin 15 gp2 i/o gpio2 pin in serial mode tx1 o when tx bit = ?0?, transmit channel (through data) output 1 pin. when tx bit = ?1?, transmit channel (daux data) output pin (default). (tx bit= ?1?: default) 16 gp3 i/o gpio3 pin in serial mode bout o block-start output pin for receiver input ?h? during first 40 flames. 17 gp4 i/o gpio4 pin in serial mode cout o c-bit output pin for receiver input 18 gp5 i/o gpio5 pin in serial mode uout o u-bit output pin for receiver input 19 gp6 i/o gpio6 pin in serial mode vout o v-bit output pin for receiver input 20 gp7 i/o gpio7 pin in serial mode 21 dvdd i digital power supply pin, 2.7v ~ 3.6v 22 vss2 i ground pin 23 mcko1 o master clock output 1 pin 24 lrck i/o channel clock pin
[ak4118a] ms1130-e-02 2009/12 - 6 - pin/function (continued) no. pin name i/o function 25 sdto o audio serial data output pin 26 bick i/o audio serial data clock pin 27 mcko2 o master clock output 2 pin 28 daux i auxiliary audio data input pin 29 xto o x'tal output pin 30 xti i x'tal input pin 31 pdn i power-down mode pin when ?l?, the ak4118a is powered-down, and all output pins go to ?l? and registers are initialized. cm0 i master clock operation mode 1 pin in parallel mode cdto o control data input pin in serial mode, iic= ?l?. 32 cad1 i control data pin in serial mode, iic= ?h?. cm1 i master clock operation mode 1 pin in parallel mode cdti i control data input pin in serial mode, iic= ?l?. 33 sda i/o control data pin in serial mode, iic= ?h?. ocks1 i output clock select 1 pin in parallel mode cclk i control data clock pin in serial mode, iic= ?l? 34 scl i control data clock pin in serial mode, iic= ?h? ocks0 i output clock select 0 pin in parallel mode csn i chip select pin in serial mode, iic=?l?. 35 cad0 i chip address 0 pin in serial mode, iic= ?h?. 36 int0 o interrupt 0 pin 37 int1 o interrupt 1 pin 38 avdd i analog power supply pin, 2.7v ~ 3.6v 39 r - external resistor pin 10k +/-1% resistor should be connected to vss3 externally. 40 vcom - common voltage output pin 0.47f capacitor should be connected to vss3 externally. 41 vss3 i ground pin 42 rx0 i receiver channel 0 pin (internal biased pin) this channel is default in serial mode. 43 nc i no connect no internal bonding. this pin should be connected to vss3. 44 rx1 i receiver channel 1 pin (internal biased pin) 45 test1 i test 1 pin. this pin should be connected to vss3. 46 rx2 i receiver channel 2 pin (internal biased pin) 47 vss4 i ground pin 48 rx3 i receiver channel 3 pin (internal biased pin) note 1. all input pins except internal biased pins (rx0-7 pins)should not be left floating.
[ak4118a] ms1130-e-02 2009/12 - 7 - absolute maximum ratings (vss1-4=0v; note 2 , note 3 ) parameter symbol min max units power supplies: analog digital input buffer avdd dvdd tvdd -0.3 -0.3 -0.3 4.6 4.6 6.0 v v v input current (any pins except supplies) iin - 10 ma input voltage (except xti pin) input voltage (xti pin) vin vinx -0.3 -0.3 tvdd+0.3 dvdd+0.3 v v ambient temperature (power applied) ta -10 70 c storage temperature tstg -65 150 c note 2. all voltages with respect to ground. note 3. vss1-4 must be connected to the same ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1-4=0v; note 2 ) parameter symbol min typ max units power supplies: analog digital input buffer avdd dvdd tvdd 2.7 2.7 dvdd 3.3 3.3 5.0 3.6 avdd 5.5 v v v note 2. all voltages with respect to ground. there is no level shifter. s/pdif receiver characteristics (ta=25 c; avdd=dvdd=2.7~3.6v; tvdd=2.7~5.5v) parameter symbol min typ max units input resistance zin 10 k input voltage vth 200 mvpp input hysteresis vhy - 50 mv input sample frequency fs 8 - 192 khz time deviation jitter ( note 4 ) - 100 - ps rms cycle - to - cycle jitter ( note 4 ) - 50 - ps rms note 4. avdd=dvdd=3.3v, tvdd=5.0v, fs=48khz
[ak4118a] ms1130-e-02 2009/12 - 8 - dc characteristics (ta=25 c; avdd=dvdd=2.7~3.6v; tvdd=2.7~5.5v; unless otherwise specified) parameter symbol min typ max units power supply current normal operation: pdn = ?h? ( note 5 ) power down: pdn = ?l? ( note 6 ) 32 10 53 100 ma a high-level input voltage low-level input voltage vih vil 70%dvdd vss2-0.3 - - tvdd 30%dvdd v v high-level output voltage (iout=-400 a) low-level output voltage (except sda pin: iout=400 a) ( sda pin: iout= 3ma) voh vol vol dvdd-0.4 - - - - - - 0.4 0.4 v v v input leakage current iin - - 10 a note 5. avdd=dvdd=3.3v, tvdd=5.0v, c l =20pf, fs=192khz, x'tal=24.576mhz, clock operation mode 2, ocks1=1, ocks0=1. avdd=7ma (typ), dvdd=25ma (typ), tvdd=10 a (typ). dvdd=36ma (typ) when the circuit of figure 23 is attached to both tx0 and tx1 pins. note 6. rx inputs are open and all dig ital input pins are held dvdd or vss2.
[ak4118a] ms1130-e-02 2009/12 - 9 - switching characteristics (ta=25 c; dvdd=avdd2.7~3.6v, tvdd=2.7~5.5v; c l =20pf) parameter symbol min typ max units master clock timing crystal resonator frequency fxtal 11.2896 24.576 mhz external clock frequency ( note 7 ) duty feclk declk 8.192 40 50 24.576 60 mhz % mcko1 output frequency duty fmck1 dmck1 4.096 40 50 24.576 60 mhz % mcko2 output frequency duty fmck2 dmck2 2.048 40 50 24.576 60 mhz % pll clock recover frequency (rx0-7) fpll 8 - 192 khz lrck frequency duty cycle fs dlck 8 45 192 55 khz % audio interface timing slave mode bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 8 ) bick ? ? to lrck edge ( note 8 ) lrck to sdto (msb) bick ? ? to sdto daux hold time daux setup time tbck tbckl tbckh tlrb tblr tlrm tbsd tdxh tdxs 80 30 30 20 20 20 20 30 30 ns ns ns ns ns ns ns ns ns master mode bick frequency bick duty bick ? ? to lrck bick ? ? to sdto daux hold time daux setup time fbck dbck tmblr tbsd tdxh tdxs -20 -15 20 20 64fs 50 20 15 hz % ns ns ns ns control interface timing (4-wire serial mode) cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 150 50 50 45 70 ns ns ns ns ns ns ns ns ns ns note 7. when feclk=8.192mhz, sampling frequency detect function (page16) is disable. note 8. bick rising edge must not occur at the same time as lrck edge.
[ak4118a] ms1130-e-02 2009/12 - 10 - switching characteristics (continued) (ta=25 c; dvdd=avdd2.7~3.6v, tvdd=2.7~5.5v; c l =20pf) parameter symbol min typ max units control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 9 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition capacitive load on bus pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto cb tsp - 1.3 0.6 1.3 0.6 0.6 0 100 - - 0.6 - 0 400 - - - - - - - 300 300 - 400 50 khz s s s s s s ns ns ns s pf ns reset timing pdn pulse width tpw 150 ns note 9. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 10. i 2 c-bus is a trademark of nxp b.v.
[ak4118a] ms1130-e-02 2009/12 - 11 - timing diagram 1/feclk teclkl vih teclkh xti vil declk = teclkh x feclk x 100 = teclkl x feclk x 100 1/fmck1 50%dvdd mcko1 tmckl1 tmckh1 dmck1 = tmckh1 x fmck1 x 100 = tmckl1 x fmck1 x 100 1/fmck2 50%dvdd mcko2 tmckl2 tmckh2 dmck2 = tmckh2 x fmck2 x 100 = tmckl2 x fmck2 x 100 1/fs lrck vih vil tlrl tlrh dlck = tlrh x fs x 100 = tlrl x fs x 100 figure 1. clock timing tlrb lrck bick sdto tbsd tblr tbckl tbckh tlrm 50%dvdd daux tdxs tdxh vih vil vih vil vih vil tbck figure 2. serial inte rface timing (slave mode)
[ak4118a] ms1130-e-02 2009/12 - 12 - lrck bick sdto tbsd tmblr 50%dvdd 50%dvdd 50%dvdd daux tdxh tdxs vih vil figure 3. serial inte rface timing (master mode) tcckl csn cclk tcds cdti tcdh tcss c0 a4 tcckh cdto hi-z r/w c1 vih vil vih vil vih vil tcck figure 4. write/read command input timing in 4-wire serial mode
[ak4118a] ms1130-e-02 2009/12 - 13 - tcsw csn cclk cdti d2 d0 tcsh cdto hi-z d1 d3 vih vil vih vil vih vil figure 5. write data input timing in 4-wire serial mode csn cclk tdcd cdto d7 d6 cdti a1 a0 d5 hi-z 50%dvdd vih vil vih vil vih vil figure 6. read data output timing 1 in 4-wire serial mode csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%dvdd vih vil vih vil vih vil figure 7. read data input timing 2 in 4-wire serial mode
[ak4118a] ms1130-e-02 2009/12 - 14 - thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 8. i 2 c bus mode timing tpw pdn vil figure 9. power down & reset timing
[ak4118a] ms1130-e-02 2009/12 - 15 - operation overview non-pcm (ac-3, mpeg, etc.) and dts-cd bitstream detection the ak4118a has a non-pcm steam auto-detection function. when the 32bit mode non-pcm preamble based on dolby ?ac-3 data stream in iec60958 interface? is detected, the auto bit goes ?1?. the 96bit sy nc code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872 and 0x4e1f. detection of this pattern will set the auto bit ?1?. once the auto is set ?1?, it will remain ?1? until 4096 frames pass through the ch ip without additional sync pattern being detected. when those preambles are detected, the burst pr eambles pc and pd that follow those sync codes are stored to registers. the ak4118a also has the dts-cd bitstream auto-detection f unction. when ak4118a detects dts-cd bitstreams, dtscd bit goes to ?1?. when the next sync code does not come within 4096 flames, dtscd bit goes to ?0? until when ak4118a detects the stream again. the ak4118a detects 14bit sync word and 16bit sync word of dts-cd bitstream. in serial control mode this detect function can be on/off by dts14 bit and dts16 bit. 192khz clock recovery the integrated low jitter pll has a wide lock range from 8khz to 192khz and the lock time is dependent on the sampling frequency and fast bit setting ( table 1 ). fast bit is useful at lower sampling frequency and is fixed to ?1? in parallel control mode. in serial control mode, the ak4118a has a sampling frequency detection function (8khz, 11.025khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz, 64khz, 88.2khz, 96khz, 176.4khz, 192khz) that uses either a clock comparison against the x?tal oscillator or the channel status information from the setting of xtl1-0 bits. in parallel control mode, the sampling frequency is detected by using the reference frequency, 24.576mhz. when the sampling frequency is more than 64khz, the fs96 pin goes to ?h?. when the sampling frequency is less than 54khz, the fs96 pin goes to ?l?. the pll loses lock when th e received sync interval is incorrect. fast bit pll lock time 0 (15 ms + 384/fs) (default) 1 (15 ms + 1/fs) table 1. pll lock time (fs: sampling frequency) master clock the ak4118a has two clock outputs, mcko1 and mcko2. the mcko2 pin output mode is selected by xmck bit. 1) xmck bit = ?0? the ak4118a has two clock outputs, mcko1 and mcko2. these clocks are derived from either the recovered clock or from the x'tal oscillator. the frequencies of the master clock outputs (mcko1 and mcko2) are set by ocks0 and ocks1 as shown in table 2 . the 512fs clock will not output when 96khz and 192khz. the 256fs clock will not output when 192khz. the mcko2 pin outputs ?l? when pll is the clock source. no. ocks1 ocks0 mcko1 mcko2 x?tal fs (max) 0 0 0 256fs ?l? 256fs 96 khz 1 0 1 256fs ?l? 256fs 96 khz 2 1 0 512fs ?l? 512fs 48 khz 3 1 1 128fs ?l? 128fs 192 khz (default) when cm1-0 bits = ?00? or ?10? and unlock bit= ?0? table 2. master clock frequency select (stereo mode)
[ak4118a] ms1130-e-02 2009/12 - 16 - when x?tal signal is the clock source, the clock can be output from the mcko1 and mcko2 pins. ( table 3 ) no. ocks1 ocks0 mcko1 mcko2 x?tal fs (max) 0 0 0 256fs 256fs 256fs 96 khz 1 0 1 256fs 128fs 256fs 96 khz 2 1 0 512fs 256fs 512fs 48 khz 3 1 1 128fs 64fs 128fs 192 khz (default) when cm1-0 bits = ?01?, ?11? or ?10? and unlock bit= ?1? table 3. master clock frequency select (stereo mode) 2) xmck bit = ?1? the mcko2 pin outputs the input clock of the xti pin regardless of ocks1-0 bit settings. div bit can set the output frequency. the mcko1 pin outputs the clock according to the cm1-0 and ocks1-0 bit settings. xmck bit div bit mcko2 clock source mcko2 frequency 1 0 x?tal x 1 1 1 x?tal x 1/2 table 4. mcko2 pin output frequency setting clock operation mode the cm0/cm1 pins (or bits) select the clock source and the data source of sdto. in mode 2, the clock source is switched from pll to x'tal when pll goes unlock state. in mode3, the clock source is fixed to x'tal, but pll is also operating and the recovered data such as c bits can be monitored. for mode2 and mode3, it is recommended that the frequency of x?tal is different from the recovered frequency from pll. mode cm1 cm0 unlock pll x'tal clock source mcko1 mcko2 sdto 0 0 0 - on on(note) pll pll ?l? rx 1 0 1 - off on x'tal x?tal x'tal daux 0 on on pll pll ?l? rx 2 1 0 1 on on x'tal x?tal x'tal daux 3 1 1 - on on x'tal x?tal x'tal daux (default) on: oscillation (power-up), off: stop (power-down) note: when the x?tal is not used as clock comparison for fs detection (i.e. xtl1/0 pi ns= ?h?), the x?tal is off. when the clock source is pll in mode 0 and mode 2, the mcko2 pin is fixed to ?l?. table 5. clock operation mode select
[ak4118a] ms1130-e-02 2009/12 - 17 - clock source the clock for the xti pin can be generated by the following methods: 1) x?tal xti xto ak4118a figure 10. x?tal mode note: external capacitance depends on the crystal oscillator (max. 30pf) 2) external clock xti xto ak4118a external clock figure 11. external clock mode note: input clock mu st not exceed dvdd. 3) fixed to the clock operation mode 0 xti xto ak4118a figure 12. off mode
[ak4118a] ms1130-e-02 2009/12 - 18 - sampling frequency and pre-emphasis detection the ak4118a has two methods for detecting the sampling frequency as follows. 1. clock comparison between recovered clock and x?tal oscillator 2. sampling frequency information on channel status those could be selected by xtl1/0 pins. and the detected frequency is reported on fs3-0 and pem bits. xtl1 xtl0 x?tal frequency l l 11.2896mhz l h 12.288mhz h l 24.576mhz h h (use channel status) (default) table 6. reference x?tal frequency xtl1-0 bit ?11? xtl1-0 bit = ?11? register output fs consumer mode ( note 12 ) professional mode ( note 13 ) fs3 fs2 fs1 fs0 clock comparison ( note 11 ) byte3 bit3,2,1,0 byte0 bit7,6 byte4 bit6,5,4,3 0 0 0 0 44.1khz 44.1khz r 3% 0 0 0 0 0 1 0 0 0 0 0 0 0 1 reserved - 0 0 0 1 (others) 0 0 1 0 48khz 48khz r 3% 0 0 1 0 1 0 0 0 0 0 0 0 1 1 32khz 32khz r 3% 0 0 1 1 1 1 0 0 0 0 0 1 0 0 22.05khz 22.05khz r 3% 0 1 0 0 0 0 1 0 0 1 0 1 0 1 11.025khz 11.025khz r 3% 0 1 1 0 24khz 24khz r 3% 0 1 1 0 0 0 0 0 0 1 0 1 1 1 16khz 16khz r 3% 1 0 0 0 88.2khz 88.2khz r 3% 1 0 0 0 0 0 1 0 1 0 1 0 0 1 8khz 8khz r 3% 1 0 1 0 96khz 96khz r 3% 1 0 1 0 0 0 0 0 1 0 1 0 1 1 64khz 64khz r 3% 1 1 0 0 176.4khz 176.4khz r 3% 1 1 0 0 0 0 1 0 1 1 1 1 1 0 192khz 192khz r 3% 1 1 1 0 0 0 0 0 1 1 note 11. at least r 3% frequency range is identified as the values in the table 7 . fs3-0 bits indicate nearer frequency for the intermediate frequency of two values. when the frequency is over the range of 32khz to 192khz, fs3-0 bits may indicate ?0001?. note 12. when consumer mode, byte3 bit3-0 are copied to fs3-0. note 13. in professional mode, fs3-0 bits are always ?0001? except for the frequencies listed in the table. table 7. sampling frequency information the pre-emphasis information is detected and reported on pem bit. this information is extracted from channel 1 at default. it can be switched to channel 2 by cs12 bit in control register. pem pre-emphasis byte 0, bits 3-5 0 off z 0x100 1 on 0x100 table 8. pem in consumer mode pem pre-emphasis byte 0, bits 2-4 0 off z 110 1 on 110 table 9. pem in professional mode
[ak4118a] ms1130-e-02 2009/12 - 19 - de-emphasis filter control the ak4118a has a digital de-emphasis filter (tc=50/15s) which corresponds to four sampling frequencies (32khz, 44.1khz, 48khz and 96khz) by iir filter. when deau bit=?1 ?, the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. the ak4118a is in this mode as default. therefore, in parallel mode, the ak4118a is always placed in this mode and the status bits in channel 1 control the de-emphasis filter. in serial mode, dem0 /1 and dfs bits can control the de-empha sis filter when deau bit is ?0?. the internal de-emphasis filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis mode is off. pem fs3 fs2 fs1 fs0 mode 1 0 0 0 0 44.1khz 1 0 0 1 0 48khz 1 0 0 1 1 32khz 1 1 0 1 0 96khz 1 (others) off 0 x x x x off table 10. de-emphasis auto control at deau = ?1? (default) pem dfs dem1 dem0 mode 1 0 0 0 44.1khz 1 0 0 1 off (default) 1 0 1 0 48khz 1 0 1 1 32khz 1 1 0 0 off 1 1 0 1 off 1 1 1 0 96khz 1 1 1 1 off 0 x x x off table 11. de-emphasis manual control at deau = ?0? system reset and power-down the ak4118a has a power-down mode for all circuits by the pdn pin, and can be partially powerd-down by pwn bit. the rstn bit initializes the register and resets the internal timing. in parallel mode, only the control by the pdn pin is enabled. the ak4118a should be reset once by bringing the pdn pin = ?l? upon power-up. pdn pin: all analog and digital circuit are placed in the power-do wn and reset mode by bringing the pdn pin= ?l?. all the registers are initialized, and clocks are stoppe d. reading/witting to the register are disabled. rstn bit (address 00h; d0): all the registers except pwn and rstn are initialized by bringing rstn bit = ?0?. the internal timings are also initialized. writing to the register is not available except pwn and rstn bits. reading to the register is disabled. pwn bit (address 00h; d1): the clock recovery part is initialized by bringing pwn bit = ?0?. in this case, clocks are stopped. the registers are not initialized and the mode settings are kept. writing and reading to the registers are enabled.
[ak4118a] ms1130-e-02 2009/12 - 20 - biphase input and through output eight receiver inputs (rx0-7) are available in serial cont rol mode. each input includes amplifier corresponding to unbalance mode and can accept the signal of 200mv or more. ips2-0 selects the receiver channel. when bcuv bit = ?1?, the block start signal, c bit and u bit can output from each pins. rxde7-0 bits indi cate the input signal status at the rx pin. when the signal is input to the rx pin, rxde bit = ?1?. ips2 ips1 ips0 input data 0 0 0 rx0 (default) 0 0 1 rx1 0 1 0 rx2 0 1 1 rx3 1 0 0 rx4 1 0 1 rx5 1 1 0 rx6 1 1 1 rx7 table 12. recovery data select b cout (or u,v) lrck (except i 2 s) c(l0) c(r0) c(l1) c(r31) c(l31) c(l32) c(r191) 1/4fs sdto l191 r191 l30 l31 r30 l0 r190 lrck (except i 2 s) sdto (except i 2 s) l30 r190 (mono mode) (normal mode) l191 r191 l0 r30 l31 lrck (i 2 s) lrck (i 2 s) figure 13. b, c, u, v output timings
[ak4118a] ms1130-e-02 2009/12 - 21 - biphase output the ak4118a outputs the data either through output (from di r) or transmitted output (dit; the data from daux is transformed to iec60958 format.) from tx1/0 pins. it is selected by dit bit. the source of the data through output from the tx0 pin is selected among rx0-8 by ops00, 01 and 02 bits, and selected by ops10, 11 and 12 bits for the tx1 pin respectively. when the ak4118a outputs daux data, v bit is controlled by the vin pin and first 5 bytes of c bit can be controlled by ct39-ct0 bits in control registers ( figure 14 ). when bit0= ?0?(consumer mode), bit20-23(audio channel) can not be controlled directly but can be controlled by ct20 bit. when the ct20 bit is ?1?, the ak4118a outputs ?1000? at c20-23 for sub frame 1(left channel) and output ?0100? at c20-23 for sub frame 2 (right channel) automatically. when ct20 bit is ?0?, the ak4118a outputs ?0000?. u bits are co ntrolled by udit bit as follows; when udit bit is ?0?, u bits are always ?0?. when udit bit is ?1?, the recovered u bits are used for dit( dir-dit loop mode of u bit). this mode is only available when pll is locked in the master mode. ops02 ops01 ops00 output data 0 0 0 rx0 (default) 0 0 1 rx1 0 1 0 rx2 0 1 1 rx3 1 0 0 rx4 1 0 1 rx5 1 1 0 rx6 1 1 1 rx7 table 13. output data select for tx0 dit ops12 ops11 ops10 output data 0 0 0 0 rx0 0 0 0 1 rx1 0 0 1 0 rx2 0 0 1 1 rx3 0 1 0 0 rx4 0 1 0 1 rx5 0 1 1 0 rx6 0 1 1 1 rx7 1 x x x daux (default) (x: don?t care) table 14. output data select for tx1 lrck ( i 2 s ) vin l0 r0 l1 daux l0 r0 l1 r191 r1 (mono mode) (normal mode) lrck (except i 2 s) l0 r0 l1 l0/r0 l1/r1 l191/r191 r1 figure 14. daux and vin input timings
[ak4118a] ms1130-e-02 2009/12 - 22 - double sampling frequency mode when mono bit = ?1?, the ak4118a outputs data in double speed according to ?single channel double sampling frequency mode? of aes3. for example, when 192khz mono da ta is transmitted or received, l/r channels of 96khz biphase data are used. in this case, one fr ame is 96khz and lrck frequency is 192khz. 1) rx when mono bit = ?1?, the ak4118a outputs mono data from sdto as follows. biphase (image) a 1 a 0 1 frame a 0 a 0 a 1 a 1 lrck (except iis) sdto 1 lrck rx mono = 1 lrck (iis) figure 15. mono mode (rx) ak4118 a lch ak4118a rch dac (ak4397) sw mclk bick lrck sdti (master) (slave) rx sdt o mcko rx sdt o figure 16. mono mode connection example (rx)
[ak4118a] ms1130-e-02 2009/12 - 23 - 2) tx when mono bit = ?1? and tlr bit = ?0?, the ak4118a outputs lch data through tx1 as biphase signal. when mono bit = ?1? and tlr bit = ?1?, then rch data is output. a 0b0 a 1b1 serial data lrck (except iis) daux 1 lrck mono = 1, tlr=0 biphase (image) a 1 a 0 1 frame tx mono = 1, tlr=1 biphase (image) b1 b0 tx lrck (iis) figure 17. mono mode (tx) ak4118a lch ak4118a rch adc (ak5394a) mclk bick lrck sdata (master) (slave) tx daux mcko tx daux xti xti xto figure 18. mono mode connection example (tx) note: in case of the connection example ( figure 18 ) or when more than one ak4118a?s are used, lrck and bick should be input after reset so that the phase of tx outputs is aligned. the ak4118a?s should be set by following sequence ( figure 19 ).
[ak4118a] ms1130-e-02 2009/12 - 24 - when powered on mode pdn pin lrck, bick stereo mode mono mode during operation mode rstn bit lrck, bick stereo mode mono mode (1) reset all the ak4118a?s by the pdn pin = ?l? ?h? or rstn bit = ?0? ?1?. (2) set all the ak4118a?s to mono mode while they are still in slave mode. (3) set one of the ak4118a to master mode so that lrck is input to all other ak4118a?s at the same time, or input lrck externally to all the ak4118a?s at the same time. figure 19. mono mode setup sequence (tx)
[ak4118a] ms1130-e-02 2009/12 - 25 - biphase signal input/output circuit rx ak4118a 0.1uf 75 figure 20. consumer input circuit (coaxial input) note: in case of coaxial input, if a coupling level to this input from the next rx input line pattern exceeds 50mv, there is a possibility to occur an incorrect operation is occured. in this case, it is possible to lower the coupling level by adding this decoupling capacitor. rx ak4118a 470 o/e optical receiver optical fiber figure 21. consumer input circuit (optical input) for coaxial input, as the input level of rx line is small in serial mode, cross-talking among rx input lines have to be avoided. for example, inserting the shield pattern among them is effective. in parallel mode, four channel inputs (rx0/1/2/3) are available and rx4-7 change to other pins for audio format control. those pins must be fixed to ?h? or ?l?. the ak4118a includes the tx output buffer. the output level meets 0.5v+/-20% using the external resistors. the t1 in the figure 22 is a transformer of 1:1. tx dvss r2 t1 75 figure 22. tx external resistor network note: when the ak4118a is in the power-down mode (pdn pin= ?l?), power supply current can be suppressed by using ac couple capacitor as following figure since the tx1 pin output becomes uncertain at power-down mode. tx1 dvss r2 t1 75
[ak4118a] ms1130-e-02 2009/12 - 26 - q-subcode buffers the ak4118a has q-subcode buffer for cd application. the ak4118a takes q-subcode into registers in following conditions. 1. the sync word (s0,s1) is c onstructed at least 16 ?0?s. 2. the start bit is ?1?. 3. those 7bits q-w follows to the start bit. 4. the distance between two st art bits are 8-16 bits. the qint bit in the control register goes ?1? when the new q-subcode differs from old one, and goes ?0? when qint bit is read. 1 2 3 4 5 6 7 8 * s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : s97 1 q97 r97 s97 t97 u97 v97 w97 0? s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : (*) number of "0" : min=0; max=8. figure 23. configuration of u- bit (cd) q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 ctrl adrs track number index q26 q27 q28 q29 q30 q31 q32 q33 q34 q35 q36 q37 q38 q39 q40 q41 q42 q43 q44 q45 q46 q47 q48 q49 minute second frame q50 q51 q52 q53 q54 q55 q56 q57 q58 q59 q60 q61 q62 q63 q64 q65 q66 q67 q68 q69 q70 q71 q72 q73 zero absolute minute absolute second q74 q75 q76 q77 q78 q79 q80 q81 q82 q83 q84 q85 q86 q87 q88 q89 q90 q91 q92 q93 q94 q95 q96 q97 absolute frame crc g(x)=x 16 +x 12 +x 5 +1 figure 24. q-subcode addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h q-subcode address / control q9 q8 ? ? ? ? q3 q2 17h q-subcode track q17 q16 ? ? ? ? q11 q10 18h q-subcode index ? ? ? ? ? ? ? ? 19h q-subcode minute ? ? ? ? ? ? ? ? 1ah q-subcode second ? ? ? ? ? ? ? ? 1bh q-subcode frame ? ? ? ? ? ? ? ? 1ch q-subcode zero ? ? ? ? ? ? ? ? 1dh q-subcode abs minute ? ? ? ? ? ? ? ? 1eh q-subcode abs second ? ? ? ? ? ? ? ? 1fh q-subcode abs frame q81 q80 ? ? ? ? q75 q74 figure 25. q-subcode register q
[ak4118a] ms1130-e-02 2009/12 - 27 - error handling the following nine events cause the int0 and int1 pins to show the status of the interrupt condition. when the pll is off (clock operation mode 1), int0 and int1 pins go to ?l?. 1. unlck : pll unlock state detect ?1? when the pll loses lock. the ak4118a loses lock when the distance between two preamble is not correct or when those preambles are not correct. 2. par : parity error or bi-phase coding error detection ?1? when parity error or bi-p hase coding error is detected, updated every sub-frame cycle. 3. auto : non-linear pcm or dts-cd bit stream detection the or function of npcm and dtscd bits is available at the auto bit. 4. v : validity flag detection ?1? when validity flag is detected . updated every sub-frame cycle. 5. audion : non-audio detection ?1? when the ?audion? bit in recovered channel st atus indicates ?1?. upda ted every block cycle. 6. stc : sampling frequency or pre-emphasis information change detection when either fs3-0 bit or pem bit is cha nged, it maintains ?1? during 1 sub-frame. 7. qint : u-bit sync flag ?1? when the q-subcode differs from the old one. updated every sync code cycle for q-subcode. 8. cint : channel status sync flag ?1? when received c bit differs from the old one. updated every block cycle. 9. dat : dat start id detect ?1? when the category code indicates ?dat? and ?d at start id? is detected. when dcnt bit is ?1?, it does not indicate ?1? even if ?dat start id? is detected again w ithin ?3841 x lrck?. when ?dat start id? is detected again after ?3840 x lrck? passed, it indicates ?1?. when dcnt bit is ?0?, it indicates ?1? every ?dat start id? detection.
[ak4118a] ms1130-e-02 2009/12 - 28 - 1. parallel control mode in parallel control mode, the int0 pin outputs the ored signal between unlck and par. the int1 pin outputs the ored signal between auto and audion. once the int0 pin goes to ?h?, it maintains ?h? fo r 1024/fs cycles after the all error events are removed. table 15 shows the state of each output pins when the int0/1 pin is ?h?. event pin unlck par auto audion int0 int1 sdto v 1 x x x l l 0 1 x x h previous data output 0 0 x x l note 14 output output x x 1 x x x x 1 h x x 0 0 note 15 l note 16 note 17 note 14. the int1 pin outputs ?l? or ?h? in accordance with the ored signal between auto and audion. note 15. the int0 pin outputs ?l? or ?h? in accor dance with the ored signal between unlck and par. note 16. the sdto pin outputs ?l?, ?previous data? or ?norma l data? in accordance with the ored signal between unlck and par. note 17. the vin pin outputs ?l? or ?normal operation? in accordance with the ored signal between par and unclk. table 15. error handling in parallel control mode (x: don?t care) 2. serial control mode in serial control mode, the int1 and int0 pins output an ored signal based on the above nine interrupt events. when masked, the interrupt event does not affect the operation of the int1-0 pins (the ma sks do not affect the registers in 07h and dat bit). once the int0 pin goes to ?h?, it remains ?h? for 1024/fs (this value can be changed with the efh1-0 bits) after all events not masked by mask bits are cleared. the int1 pin immediat ely goes to ?l? when those events are cleared. unlck, par, auto, audion and v bits in address=07h indi cate the interrupt status events above in real time. once qint, cint and dat bits goes to ?1?, it stays ?1? until the register is read. when the ak4118a loses lock, the channel status bit, user bit, pc and pd are initialized. in this initial state, the int0 pin outputs the ored signal between unlck and par bits. the int1 pin outputs the ored signal between auto and audion bits. event pin unlck par others sdto v tx 1 x x l l output 0 1 x previous data output output x x x output output output table 16. error handling in serial control mode (x: don?t care)
[ak4118a] ms1130-e-02 2009/12 - 29 - error (unlock, par,..) int1 pin sdto (unlock) mcko,bick,lrck (unlock) previous data register (par,cint,qint) hold ?1? command read 06h mcko,bick,lrck (except unlock) (fs: around 5khz) sdto (par error) hold time = 0 reset (error) sdto (others) normal operation int0 pin hold time (max: 4096/fs) register (others) free run vpin (unlock) vpin (except unlock) figure 26. int0/1 pin timing
[ak4118a] ms1130-e-02 2009/12 - 30 - int0/1 pin ="h" no ye s ye s initialize pd pin ="l" to "h" read 06h mute dac output read 06h no (each error handling) read 06h (resets registers) int0/1 pin ="h" release muting figure 27. error handling sequence example 1
[ak4118a] ms1130-e-02 2009/12 - 31 - int1 pin ="h" no ye s initialize pd pin ="l" to "h" read 06h read 06h and detect qsub= ?1? no (read q-buffer) new data is valid int1 pin ="l" qcrc = ?0? yes yes new data is invalid no figure 28. error handling sequence example (for q/cint)
[ak4118a] ms1130-e-02 2009/12 - 32 - audio serial interface format the dif0, dif1 and dif2 pins can select eight serial data formats as shown in table 17 . in all formats the serial data is msb-first, 2's compliment format. the sdto is clocked out on the falling edge of bick and the daux is latched on the rising edge of bick. bick outputs 64fs clock in mode 0-5. mode 6-7 are slave modes, and bick is available up to 128fs at fs=48khz. in the format equal or less than 20bit (mode0-2), lsbs in sub- frame are truncated. in mode 3-7, the last 4lsbs are auxiliary data ( figure 29 ). when the parity error occurs in a sub-frame, the ak4118a co ntinues to output the last normal sub-frame data from sdto repeatedly until the error is removed. when the unlo ck error occurs, the ak4118a outputs ?0? data from the sdto pin. in case of using the daux pin, the data is transformed and output from sdto. the daux pin is used in clock operation mode 1/3 and unlock state of mode 2. the input data format to daux should be left justified except in mode5 and mode7 ( table 17 ). in mode5 or mode7, both the input data format of daux and output data format of sdto are i 2 s. mode6 and mode7 are slave mode that is corresponding to the master mode of mode4 and mode5. in salve mode, lrck and bick should be fed with synchronizing to mcko1/2. 0 3 4 7 8 11 12 27 28 29 30 31 preamble aux. lsb msb vu c p sub-frame of iec60958 0 23 ak411 8 audio data (msb first) lsb msb figure 29. bit configuration lrck bick mode dif2 dif1 dif0 daux sdto i/o i/o 0 0 0 0 24bit, left justified 16bit, right justified h/l o 64fs o 1 0 0 1 24bit, left justified 18bit, right justified h/l o 64fs o 2 0 1 0 24bit, left justified 20bit, right justified h/l o 64fs o 3 0 1 1 24bit, left justified 24bit, right justified h/l o 64fs o 4 1 0 0 24bit, left justified 24bit, left justified h/l o 64fs o 5 1 0 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o 6 1 1 0 24bit, left justified 24bit, left justified h/l i 64-128fs i (default) 7 1 1 1 24bit, i 2 s 24bit, i 2 s l/h i 64-128fs i table 17. audio data format
[ak4118a] ms1130-e-02 2009/12 - 33 - lrck(0) bick ( 0:64fs ) sdto ( 0 ) 012 31 0 1 15:msb, 0:lsb lch data rch data 15 17 16 15 31 0 1 2 17 16 010 1 15 14 14 15 figure 30. mode 0 timing lrck ( 0 ) bick ( 0:64fs ) sdto ( 0 ) 012 31 0 1 23:msb, 0:lsb lch data rch data 911 10 9 31 0 1 2 11 10 010 1 12 21 20 20 21 12 22 23 22 23 figure 31. mode 3 timing lrck bick ( 64fs ) sdto ( 0 ) 012 31 0 1 23:msb, 0:lsb lch data rch data 21 23 22 21 31 0 1 2 23 22 23 22 2 24 1 0 0 1 24 21 22 23 32 23 22 figure 32. mode 4/6 timing mode4: lrck, bick (output) mode6: lrck, bick (input) lrck bick ( 64fs ) sdto ( 0 ) 012 31 0 1 23:msb, 0:lsb lch data rch data 23 22 21 31 0 1 2 23 22 23 22 24 1 0 24 32 23 25 2 0 1 21 22 23 25 figure 33. mode 5/7 timing mode5: lrck, bick (output) mode7: lrck, bick (input)
[ak4118a] ms1130-e-02 2009/12 - 34 - gpio controller the ak4118a has 8 input/output port pins. set gp0~gp7 pins by gpdr register for data direction, gpscr register for the pin level setting and gplr register for pin level reading. table 37~40 shows the pin state at setting or internal node state of gpio registers, bcu b it, tx1e/tx0e bit and vin e bit. vin gp0 register setting register read internal node vine gpe gpdr gpscr gplr vin i pin state vin gp0 pin 1 x x x l vin i vin 0 x 0 x gpi l i gpi 0 x 1 valid gpscr l o gpscr table 18. vingp0 pin and internal statement (x: don?t care) gp1 register setting register read gpe gpdr gpscr gplr pin state gp1 pin x 0 x gpi i gpi x 1 x gpscr o gpscr table 19. gp1 pin and internal statement (x: don?t care) tx0/1 gp2/3 register setting register read tx e gpe gpdr gpscr gplr pin state tx gp pin 1 x x x l o rx 0 0 x x l o l 0 1 0 x gpi i gpi 0 1 1 valid gpscr o gpscr table 20. tx0/1 gp2/3 pin and inte rnal statement (x: don?t care) b/c/u/vout gp4/5/6/7 register setting register read bcu gpe gpdr gpscr gplr pin state bcuv gp pin 1 x x x l o bcuv out 0 0 x x data hold o l 0 1 0 x gpi i gpi 0 1 1 valid gpscr o gpscr table 21. b/c/u/vout gp4/5/6/7 pin and internal statement (x: don?t care)
[ak4118a] ms1130-e-02 2009/12 - 35 - serial control interface (1). 4-wire serial control mode (iic pin= ?l?) the internal registers may be either written or read by the 4-wire p interface pins: csn, cclk, cdti & cdto. the data on this interface consists of chip address (1bit, c1 is fixed to ?0?), read/w rite (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after the 16th rising edge of cclk, after a high-to-low transition of csn. for read operations, the cdto output goes high impedance after a low-to-high transition of csn. the maximum speed of cclk is 5mhz. the pdn pin= ?l? resets the registers to their default values. when the state of psn pin is changed, the ak4118a should be reset by the pdn pin= ?l?. cdti cclk csn c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w a5 a0 d0 d1 d2 d3 cdto hi-z write cdti c1 d4 d5 d6 d7 a1 a2 a3 a4 r/w a5 a0 d0 d1 d2 d3 cdto hi-z read d4 d5 d6 d7 d0 d1 d2 d3 hi-z c1: chip address (fixed to ?0?) r/w: read/write (0:read, 1:write) a5-a0: register address d7-d0: control data figure 34. 4-wire serial control i/f timing
[ak4118a] ms1130-e-02 2009/12 - 36 - (2). i 2 c bus control mode (iic pin= ?h?) the ak4118a supports high speed mode i 2 c-bus (max: 400khz). (2)-1. data transfer in order to access any ic devices on the i2c bus, input a st art condition first, followed by a single slave address that includes the device address. ic devices on the bus compare this sl ave address with their ow n addresses and the ic device that has identical address with th e slave-address generates an acknowledgem ent. an ic device with the identical address executes either a read or write operation. after the comma nd execution, input stop condition. (2)-1-1. data change change the data on the sda line while scl line is ?l?. sda line condition must be stable and fixed while the clock is ?h?. change the data line condition betw een ?h? and ?l? only when the clock signal on the scl line is ?l?. change the sda line condition while scl line is ?h? only when the start condition or stop condition is input. scl sda data line stable : data valid change of data a llowed figure 35. data transfer (2)-1-2. start and stop condition start condition is generated by the transitio n of ?h? to ?l? on the sda line while th e scl line is ?h?. all instructions are initiated by start condition. stop condition is generated by th e transition of ?l? to ?h? on sda line while scl line is ?h?. all instructions end by stop condition. scl sda stop condition start condition figure 36. start and stop condition
[ak4118a] ms1130-e-02 2009/12 - 37 - (2)-1-3. acknowledge an external device that is sending data to the ak4118a re leases the sda line (?h?) after receiving one-byte of data. an external device that receives data from the ak4118a then sets the sda line to ?l? at the next clock. this operation is called ?acknowledgement?, and it enables verification that the data transfer has been prop erly executed. the ak4118a generates an acknowledgement upon receipt of start condition and slave address. for a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. for a read instruction, succeeded by generation of an acknowledgement, the ak4118a releases th e sda line after outputting data at the designated address, and it monitors the sda line condition. when the master side generates an acknowledgement without sending a stop condition, the ak4118a outputs data at the next address location. when no acknowledgement is generated, the ak4118a ends data output (not acknowledged). scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 37. acknowledge on the i 2 c-bus (2)-1-4. the first byte the first byte which includes the slave-address is input after the start condition is set, and a target ic device that will be accessed on the bus is selected by the slav e-address. the slave-address is configur ed with the upper 7- bits. data of the upper 5-bits is ?00100?. the next 2 bits are address bits that select the desired ic which are set by the cad1 and cad0 pins. when the slave-address is inputted, an external device that has the identical device address generates an acknowledgement and instructions ar e then executed. the 8th bit of the first byte (lowest bit) is allocated as the r/w bit. when the r/w bit is ?1?, the read instruction is executed , and when it is ?0?, the write instruction is executed. 0 0 1 0 0 cad1 cad0 r/w (those cad1/0 should match with cad1/0 pins.) figure 38. the first byte
[ak4118a] ms1130-e-02 2009/12 - 38 - (2)-2. write operations set r/w bit = ?0? for the write operation of the ak4118a. after receipt the start condition and the first byte, the ak4118a generates an acknowledge, and awaits the second byte (register address). the second byte consis ts of the address for control registers of the ak4118a. the format is msb first, and those most significant 3-bits are ?don?t care?. 0 0 a5 a4 a3 a2 a1 a0 (*: don?t care) figure 39. the second byte after receipt the second byte, the ak411 8a generates an acknowledge, and awaits the third byte. those data after the second byte contain control data. the format is msb first, 8bits. d7 d6 d5 d4 d3 d2 d1 d0 figure 40. byte structure after the second byte the ak4118a is capable of more than one byte write operation in one sequence. after receipt of the third byte, the ak4118a generates an ack nowledge, and awaits the next data again. the master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. after the receipt of each data, the internal 5bits a ddress counter is incremented by one, and th e next data is taken into next address automatically. if the address exceed 1fh prior to generating th e stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. sda s t a r t a c k a c k s slave a ddress a c k registe r a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) figure 41. write operation
[ak4118a] ms1130-e-02 2009/12 - 39 - (2)-3. read operations set r/w bit = ?1? for the read operation of the ak4118a. after transmission of a data, the master can read next address?s data by ge nerating the acknowledge instead of terminating the write cycle after the receipt the first data word. after the receipt of each data, the internal 5bits address counter is incremented by one, and the ne xt data is taken into next address au tomatically. if the address exceed 1fh prior to generating the stop condition, the addr ess counter will ?ro ll over? to 00h and the previ ous data will be overwritten. the ak4118a supports two basic read operations: current address read and random read. (2)-3-1. current address read the ak4118a contains an internal addre ss counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address ?n?, the next current read operation would access data from the address ?n+1?. after receipt of the slave addr ess with r/w bit set to ?1?, the ak4118a generates an acknowledge, transmits 1byte data which address is set by the internal addr ess counter and increments the internal address counter by 1. if the master does not generate an acknowledge but generate the stop condition, the ak4118a discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n) data(n+1) p s t o p data(n+x) a c k data(n+2) figure 42. current address read (2)-3-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues start condition, slave address(r/w=?0?) and then the register address to read. after the register address?s acknowledge, the master immediately reissues start condition and the slave address with the r/w bit set to ?1?. then the ak4118a generates an acknowledge, 1byte data and in crements the internal address counter by 1. if the master does not generate an acknowledge but generate the stop condition, the ak4118a discontinues transmission. sda s t a r t a c k a c k ss s t a r t slave a ddress word a ddress(n) slave a ddress a c k data(n) a c k p s t o p data(n+x) a c k data(n+1) figure 43. random read
[ak4118a] ms1130-e-02 2009/12 - 40 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clk & power down control cs12 bcu cm1 cm0 ocks1 ocks0 pwn rstn 01h format & de-em control mono dif2 dif1 dif0 deau dem1 dem0 dfs 02h input/ output control 0 tx1e ops12 ops11 ops10 tx0e ops02 ops01 ops00 03h input/ output control 1 efh1 efh0 udit tlr dit ips2 ips1 ips0 04h int0 mask mqit0 maut0 mcit0 mulk0 mdts0 mpe0 maud0 mpar0 05h int1 mask mqit1 maut1 mcit1 mulk1 mdts1 mpe1 maud1 mpar1 06h receiver status 0 qint auto cint unlck dtscd pem audion par 07h receiver stat us 1 fs3 fs2 fs1 fs0 0 v qcrc ccrc 08h rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 09h rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ah rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0bh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0ch rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 0dh tx channel status byte 0 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 0eh tx channel status byte 1 ct15 ct14 ct13 ct12 ct11 ct10 ct9 ct8 0fh tx channel status byte 2 ct23 ct22 ct21 ct20 ct19 ct18 ct17 ct16 10h tx channel status byte 3 ct31 ct30 ct29 ct28 ct27 ct26 ct25 ct24 11h tx channel status byte 4 ct39 ct38 ct37 ct36 ct35 ct34 ct33 ct32 12h burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 13h burst preamble pc byte 1 pc15 pc 14 pc13 pc12 pc11 pc10 pc9 pc8 14h burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 15h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 16h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 17h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 18h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 19h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 1ah q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 1bh q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 1ch q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 1dh q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 1eh q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1fh q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74
[ak4118a] ms1130-e-02 2009/12 - 41 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 20h gpe gpe rxdete vine fast exckmd dcnt dts16 dts14 21h gpdr io7 io6 io5 io4 io3 io2 io1 io0 22h gpscr cs7 sc6 cs5 sc4 sc3 sc2 sc1 cs0 23h gplr gpl7 gpl 6 gpl 5 gpl 4 gpl 3 gpl 2 gpl 1 gpl 0 24h dat mask & dts detect xmck div med1 mdr0 mstc1 mstc0 mdat1 mdat0 25h rx detect rxde7 rxde6 r xde5 rxde4 rxde3 rxde2 rxde1 rxde0 26h stc & dat detect 0 0 0 0 0 0 stc dat 27h rx channel status byte 5 0 0 0 0 0 0 cr41 cr40 28h tx channel status byte 5 0 1 0 0 0 0 ct41 ct40 note: when the pdn pin goes ?l?, the registers are initialized to their default values. when rstn bit goes ?0?, the internal timing is reset an d the registers are initialized to their default values. all data can be written to the register even if pwn bit is ?0?.
[ak4118a] ms1130-e-02 2009/12 - 42 - register definitions reset & initialize addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clk & power down control cs12 bcu cm1 cm0 ocks1 ocks0 pwn rstn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 0 1 1 rstn: timing reset & register initialize 0: reset & initialize 1: normal operation pwn: power down 0: power down 1: normal operation ocks1-0: master clock frequency select cm1-0: master clock operation mode select bcu: block start & c/u output mode when bcu=1, the three output pins(bout, cout, uout) become to be enabled. the block signal goes high at the start of frame 0 and remains high until the end of frame 31. cs12: channel status select 0: channel 1 1: channel 2 selects which channel status is used to derive c-bit buffers, audion, pem, fs3, fs2, fs1, fs0, pc and pd. the de-emphasis filter is controlled by channel 1 in the parallel mode. format & de-emphasis control addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h format & de-em control mono dif2 dif1 dif0 deau dem1 dem0 dfs r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 1 0 1 0 1 0 dfs: 96khz de-emphasis control dem1-0: 32, 44.1, 48khz de-emphasis control ( table 11 ) deau: de-emphasis auto detect enable 0: disable 1: enable dif2-0: audio data format control ( table 17 ) mono: double sampling frequency mode enable 0: stereo mode 1: mono mode
[ak4118a] ms1130-e-02 2009/12 - 43 - input/output control addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h input/ output control 0 tx1e ops12 ops11 ops10 tx0e ops02 ops01 ops00 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 1 0 0 0 ops02-00: output through data select for tx0 pin ops12-10: output through data select for tx1 pin tx0e: tx0 output enable 0: disable. tx0 outputs ?l?. 1: enable tx1e: tx1 output enable 0: disable. tx1 outputs ?l?. 1: enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h input/ output control 1 efh1 efh0 udit tlr dit ips2 ips1 ips0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 1 0 0 0 ips2-0: input recovery data select dit: through data/transmit data select for tx1 pin 0: through data (rx data). 1: transmit data (daux data). tlr: double sampling frequency mode channel select for dit(stereo) 0: l channel 1: r channel udit: u bit control for dit 0: u bit is fixed to ?0? 1: recovered u bit is used for dit (loop mode for u bit) efh1-0: interrupt 0 pin hold count select 00: 512 lrck 01: 1024 lrck 10: 2048 lrck 11: 4096 lrck
[ak4118a] ms1130-e-02 2009/12 - 44 - mask control for int0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h int0 mask mqi0 mat0 mci0 mul0 mdts0 mpe0 man0 mpr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 0 1 1 1 0 mpr0: mask enable for par bit man0: mask enable for audn bit mpe0: mask enable for pem bit mdts0: mask enable for dtscd bit mul0: mask enable for unlock bit mci0: mask enable for cint bit mat0: mask enable for auto bit mqi0: mask enable for qint bit 0: mask disable 1: mask enable mask control for int1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h int1 mask mqi1 mat1 mci1 mul1 mdts1 mpe1 man1 mpr1 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 1 1 0 1 0 1 mpr1: mask enable for par bit man1: mask enable for audn bit mpe1: mask enable for pem bit mdts1: mask enable for dtscd bit mul1: mask enable for unlock0 bit mci1: mask enable for cint bit mat1: mask enable for auto bit mqi1: mask enable for qint bit 0: mask disable 1: mask enable
[ak4118a] ms1130-e-02 2009/12 - 45 - receiver status 0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h receiver status 0 qint auto cint unlck dtscd pem audion par r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 par: parity error or biphase error status 0:no error 1:error it is ?1? if parity error or biphase error is detected in the sub-frame. audion: audio bit output 0: audio 1: non audio this bit is made by encoding channel status bits. pem: pre-emphasis detect. 0: off 1: on this bit is made by encoding channel status bits. dtscd: dts-cd auto detect 0: no detect 1: detect unlck: pll lock status 0: locked 1: unlocked cint: channel status buffer interrupt 0: no change 1: changed auto: non-pcm auto detect 0: no detect 1: detect qint: q-subcode buffer interrupt 0: no change 1: changed qint, cint and par bits are initialized when 06h is read. receiver status 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h receiver stat us 1 fs3 fs2 fs1 fs0 0 v qcrc ccrc r/w rd rd rd rd rd rd rd rd default 0 0 0 1 0 0 0 0 ccrc: cyclic redundancy check for channel status 0:no error 1:error qcrc: cyclic redundancy check for q-subcode 0:no error 1:error v: validity of channel status 0:valid 1:invalid fs3-0: sampling frequency detection ( table 7 )
[ak4118a] ms1130-e-02 2009/12 - 46 - receiver channel status addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 09h rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ah rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0bh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0ch rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 27h rx channel status byte 5 0 0 0 0 0 0 cr41 cr40 r/w rd default not initialized cr41-0: receiver channel status byte 5-0 transmitter channel status addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh tx channel status byte 0 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 0eh tx channel status byte 1 ct15 ct14 ct13 ct12 ct11 ct10 ct9 ct8 0fh tx channel status byte 2 ct23 ct22 ct21 ct20 ct19 ct18 ct17 ct16 10h tx channel status byte 3 ct31 ct30 ct29 ct28 ct27 ct26 ct25 ct24 11h tx channel status byte 4 ct39 ct38 ct37 ct36 ct35 ct34 ct33 ct32 28h tx channel status byte 5 0 1 0 0 0 0 ct41 ct40 r/w r/w default 0 ct41-0: transmitter channel status byte 5-0 burst preamble pc/pd in non-pcm encoded audio bitstreams addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 13h burst preamble pc byte 1 pc 15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 14h burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 15h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 r/w rd default not initialized pc15-0: burst preamble pc byte 0 and 1 pd15-0: burst preamble pd byte 0 and 1
[ak4118a] ms1130-e-02 2009/12 - 47 - q-subcode buffer addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 17h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 18h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 19h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 1ah q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 1bh q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 1ch q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 1dh q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 1eh q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1fh q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 r/w rd default not initialized gpio control addr register name d7 d6 d5 d4 d3 d2 d1 d0 20h gpe gpe rxdete vine fast exckmd dcnt dts16 dts14 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 1 1 0 1 1 1 dts14: dts-cd 14bit sync word detect 0: disable 1: enable (default) dts16: dts-cd 16bit sync word detect 0: disable 1: enable (default) dcnt: start id counter 0: disable 1: enable (default) exckmd: x?tal oscillator setting 0: power up (default) 1: power down fast: pll lock time select ( table 1 ) 0: (15ms + 384/fs) (default) 1: (15ms + 1/fs) vine: vin input enable 0: disable 1: enable (default) rxdete: rx input detect enable 0: disable 1: enable (default) gpe: gpio mode enable 0: gpio mode disable (default) 1: gpio mode enable gpio mode for gp2-7 pins is enabled when gpe bit= ?1? and bcu bit= tx1e bit= tx0e bit= ?0?. the gp0 pin is in gpio mode regardless of the state of gpe bit when vine bit= ?0?. the gp1 pin is always in gpio mode.
[ak4118a] ms1130-e-02 2009/12 - 48 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 21h gpdr io7 io6 io5 io4 io3 io2 io1 io0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 io7-0: gpio pin input/output setting 0: input (default) 1: output addr register name d7 d6 d5 d4 d3 d2 d1 d0 22h gpscr sc7 sc6 sc5 sc4 sc3 sc2 sc1 sc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 sc7-0: gpio pin output level setting 0: ?l? (default) 1: ?h? this is effective only when the pin setting is in output mode (21h: gpdr= ?1?). actual pin level can be read by gplr register. addr register name d7 d6 d5 d4 d3 d2 d1 d0 23h gplr gpl7 gpl6 gpl5 gpl4 gpl3 gpl2 gpl1 gpl0 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 gpd7-0: gpio pin input level read glp7-0 bits are read only regist er that can read the input signal level of corresponding gpio pins (gp7-0 pins). gpio mode is enabled gp2-7 pins can read the input signal level when gpe bit = ?1? and bcu bit = tx1e bit = tx0e bit = ?0?. when vine bit = ?0?, gpio mode of the gp1 pin is enabled and gplo bit can read the input signal leve l. gpl1 bit can always read the input signal level of the gp1 pin. gpl2-7 bits and gpl0 bit are always ?0? when gpio mode is disable.
[ak4118a] ms1130-e-02 2009/12 - 49 - dat mask & dts detect addr register name d7 d6 d5 d4 d3 d2 d1 d0 24h dat mask & dts detect xmck div mrdt1 mrdt0 mstc1 mstc0 mdat1 mdat0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 1 1 1 1 1 mdat0: mask enable for dat bit 0: mask disable 1: mask enable (default) when the mask is enabled ?1?, dat stat e is not reflected on to the int0 pin. mdat1: mask enable for dat bit 0: mask disable 1: mask enable (default) when the mask is enabled ?1?, dat stat e is not reflected on to the int1 pin. mstc0: mask enable for stc bit 0: disable 1: enable (default) when the mask is enabled ?1?, stc stat e is not reflected on to the int0 pin. mstc1: mask enable for stc bit 0: disable 1: enable (default) when the mask is enabled ?1?, stc stat e is not reflected on to the int1 pin. mrdt0: mask enable for rx detect 0: disable 1: enable (default) when the mask is enabled ?1?, rx input detection resault is not reflected on to the int0 pin. mrdt1: mask enable for rx detect 0: disable 1: enable (default) when the mask is enabled ?1?, rx input detection resault is not reflected on to the int1 pin. div: mcko2 frequency dividing ratio in x?tal mode ( table 4 ) 0: x1 (default) 1: x 1/2 xmck: mcko2 output setting ( table 4 ) 0: setting by cm1-0 bits and ocks1-0 bits (default) 1: fixed in x?tal mode rx detect addr register name d7 d6 d5 d4 d3 d2 d1 d0 25h rx detect rxde7 rxde6 r xde5 rxde4 rxde3 rxde2 rxde1 rxde0 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 rxde7-0: the rx pin input detect 0: no detect 1: detect when the rxdete bit is set to ?0?, the input detection functio n is disabled and the register is fixed to ?0?. when the unused rx pin is open, the ak4118a may not be able to detect the input signal correctly. the unused rx pin should be connected to the gnd.
[ak4118a] ms1130-e-02 2009/12 - 50 - stc & dat detect addr register name d7 d6 d5 d4 d3 d2 d1 d0 26h stc & dat detect 0 0 0 0 0 0 stc dat r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 dat: dat start id detect 0: no detect 1: detect dat bit is initialized when addr= 26h is read. stc: change detection of sampling frequency and pre-emphasis information 0: no detect 1: detect when fs3-0 bits or pem bit is changed, stc bit goes to ?1?. stc bit is initialized when addr=26h is read. burst preambles in non-pcm bitstreams 0 16 bits of bitstream 34 7 811 12 27 28 29 30 31 preamble aux. lsb msb v u c p sub-frame of iec60958 015 pa pb pc pd burst_payload stuffing repetition time of the burst figure 44. data structure in iec60958 preamble word length of field contents value pa 16 bits sync word 1 0xf872 pb 16 bits sync word 2 0x4e1f pc 16 bits burst info see table 23 pd 16 bits length code numbers of bits table 22. burst preamble words
[ak4118a] ms1130-e-02 2009/12 - 51 - bits of pc value contents repetition time of burst in iec60958 frames 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 data type null data dolby ac-3 data reserved pause mpeg-1 layer1 data mpeg-1 layer2 or 3 data or mpeg-2 without extension mpeg-2 data with extension mpeg-2 aac adts mpeg-2, layer1 low sample rate mpeg-2, layer2 or 3 low sample rate reserved dts type i dts type ii dts type iii atrac atrac2/3 reserved 4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 5, 6 0 reserved, shall be set to ?0? 7 0 1 error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors 8-12 data type dependent info 13-15 0 bit stream number, shall be set to ?0? table 23. fields of burst info pc
[ak4118a] ms1130-e-02 2009/12 - 52 - non-pcm bitstream timing 1) when non-pcm preamble data is not coming within 4096 frames, pa pc 1 pd 1 pb pa pc 2 pd 2 pb pa pc 3 pd 3 pb ?0? pc 1 pc 2 ?0? pd 1 pd 2 pd 3 pc 3 pdn pin bit stream a uto bit pc register pd registe r repetition time >4096 frames figure 45. timing example 1 2) when non-pcm bitstream stops (when mulk0 bit = ?0?), pa pc 1 pd 1 pb stop pa pc n pd n pb pc 0 pc 1 pd 0 pd 1 pd n pc n int0 pin bit stream a uto bit pc register pd registe r int0 hold time 2~3 syncs (b,m or w) <20ms (lock time) [ak4118a] ms1130-e-02 2009/12 - 53 - system design figure 47 shows the example of system c onnection diagram for serial mode. r microcontroller rx 3 rx4 1 2 3 4 5 6 7 8 9 11 10 nc test2 rx6 vss1 rx7 iic p /s n xtl0 ( * ) xtl1 ( * ) csn vss 4 rx 2 n c rx 0 vss 3 vco m avdd tvdd int0 1 3 14 15 16 17 18 19 20 21 22 23 tx1 nc tx0 b u v dvdd vss2 m c k o 1 cc lk cdti cdto pd n xti xto daux mcko2 bick ak4118a c test1 rx1 rx5 36 35 34 33 32 31 30 29 2 8 26 27 4 8 47 46 45 44 43 42 41 40 39 38 12 vin 24 lr c k sdto 25 in t1 37 (spdif sources) (spdif sources) +3.3v analog supply 10f 0.1f +3.3v digital supply codec (ak4626a) dsp +3.3v to +5v digital supply 10f 0.1f (spdif out) (shield) sdto mclk bick lr ck sdti1 (micro controller) (microcontroller) 0.1f 10f sdti 2 sdti3 x?tal=11.2896mhz r c c analog ground digital ground + + + 10k ohm figure 47. typical connec tion diagram (serial mode) notes - for xtl0 and xtl1settings, refer to the table 5. - ?c? value is dependent on the crystal. - vss1-4 must be connected the same ground plane. - digital signals, especially clocks, should be kept away from the r pin in order to avoid an effect to the clock jitter performance.
[ak4118a] ms1130-e-02 2009/12 - 54 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp(unit:mm) 0.10 37 24 25 36 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.5 0.09~0.20 0.3~0.75 material & lead finish package molding compound: epoxy, halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ak4118a] ms1130-e-02 2009/12 - 55 - marking ak4118aeq xxxxxxx 1 xxxxxxxx: date code identifier date (yy/mm/dd) revision reason page contents 09/10/06 00 first edition 09/10/21 01 error correction 39 register map addr 11h, d6~d1: ct39 ct38 ~ 33 45 transmitter channel status addr 28h, d0: ct42 ct40 09/12/24 02 description 4 ? compatibility with ak4118? was added. addition 16 a description about table 3 was added. revision history
[ak4118a] ms1130-e-02 2009/12 - 56 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of th e above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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